1. Field of the Invention
The present invention relates to an A/D conversion circuit and a solid-state imaging device using the same.
The application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2012-108365, filed May 10, 2012, the entire contents of which are incorporated herein.
2. Description of Related Art
As an example of an A/D conversion circuit used in a solid-state imaging device of the related art, a configuration illustrated in FIG. 9 has been known (for example, see Japanese Unexamined Patent Application, First Publication No. 2009-38726, and Japanese Unexamined Patent Application, First Publication No. 2009-38781). Firstly, the configuration of the A/D conversion circuit illustrated in FIG. 9 will be described. The A/D conversion circuit illustrated in FIG. 9 includes a phase shift portion 101, a comparison circuit 102, a latch portion 103, a counter circuit 104, and a buffer circuit 105.
The phase shift portion 101 includes a plurality of delay units DU[0] to DU[7] that delay and output an input signal. A start pulse φStartP is input to the first delay unit DU[0]. The comparison circuit 102 receives an analog signal φSignal, which is an object of time detection, and a ramp wave φRamp that decreases with the lapse of time, and outputs a signal φCOMP_OUT indicating a result obtained by comparing the analog signal φSignal with the ramp wave φRamp. The latch portion 103 includes latch circuits L_0 to L_7 that latch logical states of output signals φCK0 to φCK7 of each of the delay units DU[0] to DU[7] of the phase shift portion 101. The counter circuit 104 performs counting based on the output signal φCK7 of the delay unit DU[7] of the phase shift portion 101.
The comparison circuit 102 generates a time interval (the size in a time axial direction) according to the amplitude of the analog signal φSignal. The buffer circuit 105 is an inversion buffer circuit that inverts and outputs an input signal. Hereinafter, in order to facilitate the understanding of the description of the present specification, the buffer circuit 105 has a configuration of the inversion buffer circuit.
The latch circuits L_0 to L_7 constituting the latch portion 103 are in an enable (valid) state when an output signal φHOLD of the buffer circuit 105 is High, and output the output signals φCK0 to φCK7 of the delay units DU[0] to DU[7] as is. Furthermore, the latch circuits L_0 to L_7 are in a disable (invalid) state when the output signal φHOLD of the buffer circuit 105 is transitioned from High to Low, and latch logic states according to the output signals φCK0 to φCK7 of the delay units DU[0] to DU[7] at that time.
A count latch circuit, which latches a logic state of a count result of the counter circuit 104, is not illustrated. However, the counter circuit having a latch function is used, so that the counter circuit 104 serves as the count latch circuit.
Next, an operation of the related art will be described. FIG. 10 illustrates the operation of an A/D conversion circuit according to the related art. Firstly, at a timing (a first timing) related to the comparison start of the comparison circuit 102, as the start pulse φStartP, a clock of a cycle, which approximately coincides with the delay time (the sum of delay times of the eight delay units DU[0] to DU[7]) of the phase shift portion 101, is input to the phase shift portion 101.
In this way, the phase shift portion 101 starts to operate. The delay unit DU[0] constituting the phase shift portion 101 delays the start pulse φStartP and outputs the output signal φCK0. The delay units DU[1] to DU[7] constituting the phase shift portion 101 delay output signals of delay units of a previous stage and output the output signals φCK1 to φCK7, respectively. The output signals φCK0 to φCK7 of the delay units DU[0] to DU[7] are input to the latch circuits L_0 to L_7 of the latch portion 103. The latch circuit L_7 outputs the output signal φCK7 of the input delay unit DU[7] to the counter circuit 104 as is.
The counter circuit 104 performs a counting operation based on the output signal φCK7 of the delay unit DU[7], which is output from the latch circuit L_7 of the latch portion 103. In the counting operation, a count value is increased or decreased at the rise or the fall of the output signal φCK7. At a timing (a second timing) at which the analog signal φSignal approximately coincides with the ramp wave φRamp, the output signal φCOMP_OUT of the comparison circuit 102 is inverted. Moreover, at a timing (a third timing) after the lapse of a predetermined delay time applied to the input signal in the buffer circuit 105, the output signal φHOLD of the buffer circuit 105 becomes a Low state.
In this way, the latch circuits L_0 to L_7 become a disable state. At this time, logic states according to the output signals φCK0 to φCK7 of the delay units DU[0] to DU[7] are latched in the latch circuits L_0 to L_7. The counter circuit 104 latches a count value when the latch circuit L_7 stops operating. By the logic state latched in the latch portion 103 and the count value latched in the counter circuit 104, digital data corresponding to the analog signal φSignal is obtained.
In accordance with the A/D conversion circuit according to the related art, it is possible to obtain digital data corresponding to the time interval according to the voltage of the analog signal φSignal. That is, it is possible to obtain the digital data corresponding to the analog signal φSignal.